Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock

We reduce the test time of external test applied from an automatic test equipment (ATE) by speeding up low activity cycles without exceeding the specified peak power budget. An activity monitor is implemented as hardware or as presimulated and stored test data for this purpose. The achieved test time reduction depends upon the input and output activity factors, α_in and α_out, of the scan chain. When on-circuit built-in hardware control is used, test time reductions of about 50% and 25% are possible for vectors with low input activity α_in ≈ 0 and moderate input activity α_in = 0.5, respectively, in ITC02 benchmark circuits. When stored pre-simulated test data is used, test time reduction of up to 99% is shown for vectors with low input and output activities.