Domain Coverage Metric for SoC Validation

Author

Wang Xuexiang ; Yang Jun

Author_Institution

Nat. ASIC Syst. Eng. Res. Center, Sourtheast Univ., Nan Jing

fYear

2009

fDate

28-29 April 2009

Firstpage

1

Lastpage

4

Abstract

The importance of System-On-Chip (SoC) validation continues to grow with the increase of design size. How to measure the completeness and quality of validation approach? An innovative domain coverage metric is proposed in this paper. Domain methodology is based on a geometrical analysis of the domain boundary and takes advantage of the fact that point on or near the boundary is most sensitive to domain errors. The coverage tool has been implemented using Verilog procedural interface (VPI) and has been applied to validation of SoC under design. Results show that the domain coverage can detect many design faults that statement and path coverage can not.

Keywords

fault diagnosis; geometry; hardware description languages; logic design; system-on-chip; SoC validation; Verilog procedural interface; design fault detection; domain coverage metric; geometrical analysis; system-on-chip; Acceleration; Application specific integrated circuits; Circuit faults; Emulation; Fault detection; Formal verification; Hardware design languages; System-on-a-chip; Systems engineering and theory; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Testing and Diagnosis, 2009. ICTD 2009. IEEE Circuits and Systems International Conference on

Conference_Location

Chengdu

Print_ISBN

978-1-4244-2587-7

Type

conf

DOI

10.1109/CAS-ICTD.2009.4960810

Filename

4960810