A low-power low-noise amplifier in 0.35-μm SOI CMOS technology

Author

Zencir, Ertan ; Dogan, Numan S. ; Arvas, Ercument ; Ketel, Mohammed

Author_Institution

Electr. & Comput. Eng. Dept, North Carolina A&T State Univ., Greensboro, NC, USA

Volume

1

fYear

2003

fDate

25-28 May 2003

Abstract

A low-power 435-MHz single-ended low-noise amplifier was implemented in a 0.35-μm silicon on insulator (SOI) CMOS technology. The SOI CMOS LNA has a simulated noise figure of 0.6 dB, input 1-dB compression point of -12.5 dBm, input third-order intercept point of -5 dBm, and small-signal gain of 22 dB. Total power dissipation is 10 mW from a 2.5-V supply. LNA chip area is 1.4 mm × 0.58 mm. Due to high-resistivity silicon substrate and buried oxide isolation, SOI CMOS technology offers significant performance improvements for mixed-signal VLSI and RF/Microwave integrated circuits.

Keywords

CMOS analogue integrated circuits; UHF amplifiers; UHF integrated circuits; integrated circuit noise; low-power electronics; silicon-on-insulator; 0.35 micron; 0.6 dB; 10 mW; 2.5 V; 22 dB; 435 MHz; RF integrated circuit; SOI CMOS technology; Si; buried oxide isolation; high-resistivity silicon substrate; input compression point; input third-order intercept point; low-power low-noise amplifier; mixed-signal VLSI; noise figure; power dissipation; small-signal gain; CMOS technology; Gain; Integrated circuit technology; Isolation technology; Low-noise amplifiers; Microwave technology; Noise figure; Power dissipation; Silicon on insulator technology; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205558

Filename

1205558