DocumentCode
3533505
Title
Specific Design and Optimization of JTAG IP Core
Author
Zhang, Xiaobo ; Jiang, Yanfeng ; Ju, Jiaxin
Author_Institution
Dept. of Microelectron., North China Univ. of Technol., Beijing
fYear
2009
fDate
28-29 April 2009
Firstpage
1
Lastpage
4
Abstract
A JTAG IP core based on IEEE1149.1 standard has been reported here, including its design and implementation. It has been described using synthesized Verilog HDL language. Simulation demonstration has also been made and the result has been synthesized. It has been demonstrated that the IP core design is feasibility. Moreover, based on the characteristic of DFT using JTAG standard, some improvements on the JTAG structure are proposed to get an optimized result.
Keywords
automatic testing; design for testability; hardware description languages; integrated circuit testing; DFT; IEEE1149.1; JTAG IP core; Verilog HDL language; Automatic testing; Built-in self-test; Circuit testing; Design optimization; Electronic equipment testing; Hardware design languages; Integrated circuit testing; Logic testing; Production facilities; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Testing and Diagnosis, 2009. ICTD 2009. IEEE Circuits and Systems International Conference on
Conference_Location
Chengdu
Print_ISBN
978-1-4244-2587-7
Type
conf
DOI
10.1109/CAS-ICTD.2009.4960877
Filename
4960877
Link To Document