DocumentCode :
3533575
Title :
IP protection in Partially Reconfigurable FPGAs
Author :
Kepa, Krzysztof ; Morgan, Fearghal ; Kosciuszkiewicz, Krzysztof
Author_Institution :
Dept. of Electron. Eng., Nat. Univ. of Ireland, Galway, Galway, Ireland
fYear :
2009
fDate :
Aug. 31 2009-Sept. 2 2009
Firstpage :
403
Lastpage :
409
Abstract :
As FPGA technology and related EDA tools develop, design IP protection and licensing requires increasing consideration. The current multi-player, partial-reconfiguration (PR) design flow does not facilitate bitstream-level IP core license enforcement, e.g, time-limited or pay-per-use. This paper proposes the use of a secure reconfigurable controller (SeReCon) for accounting of IP core usage, e.g. total runtime, no. of activations etc, in a PR system. This paper extends the reported SeReCon root-of-trust to support license enforcement within the PR flow and to facilitate confidentiality of the IP core during the PR system life-cycle. A prototype IP-aware SeReCon demonstrator, implemented on Virtex-5 and supporting reconfiguration of a PCIe accelerator with cryptographic IP cores is described.
Keywords :
cryptography; field programmable gate arrays; industrial property; EDA tools; IP protection; IP-aware SeReCon demonstrator; PCIe accelerator; PR system life-cycle; SeReCon root-of-trust; Virtex-5; cryptographic intellectual property cores; field programmable gate arrays; partial-reconfiguration design flow; partially reconfigurable FPGA; secure reconfigurable controller; Communication system control; Control systems; Cryptography; Design engineering; Field programmable gate arrays; Licenses; Protection; Prototypes; Runtime; Security;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on
Conference_Location :
Prague
ISSN :
1946-1488
Print_ISBN :
978-1-4244-3892-1
Electronic_ISBN :
1946-1488
Type :
conf
DOI :
10.1109/FPL.2009.5272250
Filename :
5272250
Link To Document :
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