Clock duplicity for high-precision timestamping in Gigabit Ethernet

Author

Nicolau, Carles ; Sala, Dolors ; Canto, Enrique

Author_Institution

Dept. of Inf., & Commun. Technol., Univ. Pompeu Fabra, Spain

fYear

2009

fDate

Aug. 31 2009-Sept. 2 2009

Firstpage

379

Lastpage

384

Abstract

Hardware-timestamping is essential for achieving tight synchronization in networking applications. This mechanism is selectively used on few high-cost tailored systems. Actual muP-based implementations fail on deterministic timestamp retrieval and insertion inside the message. This problem degrades significantly the synchronization between network nodes. This paper describes the analysis, implementation, and evaluation of a HW-timestamping technique for minimal-latency timestamping at Gigabit Ethernet using a low-cost off-the-shelf FPGA board. The effectiveness of the method is validated through a point-to-point synchronization scheme achieving a best-case synchronization accuracy of 150 ns.

Keywords

clocks; field programmable gate arrays; local area networks; synchronisation; Gigabit Ethernet; clock duplicity; deterministic timestamp retrieval; high-precision hardware timestamping; low-cost off-the-shelf FPGA board; minimal-latency timestamping; muP-based implementation; synchronization; Clocks; Counting circuits; Degradation; Delay; Ethernet networks; Field programmable gate arrays; Frequency synchronization; Logic; Protocols; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on

Conference_Location

Prague

ISSN

1946-1488

Print_ISBN

978-1-4244-3892-1

Electronic_ISBN

1946-1488

Type

conf

DOI

10.1109/FPL.2009.5272258

Filename

5272258