A high speed low input current low voltage CMOS current comparator

Author

Moolpho, K. ; Ngarmnil, J. ; Sitjongsataporn, S.

Author_Institution

Electron. Eng. Dept., Mahanakorn Univ. of Technol., Bangkok, Thailand

Volume

1

fYear

2003

fDate

25-28 May 2003

Abstract

A new high speed low input current comparator is proposed in this paper. Based on a simple negative feedback scheme around the transimpedance stage, with an emphasis on a very large loop-gain, the transformed voltage signal is maintained at the lowest swing that results in a speed improvement. On a 0.25 μm TSMC CMOS process, simulation results demonstrate propagation delays of. 3.6 ns with ±100 nA input current and 1.5 Volts power supply, while the smallest input current is ±50 pA. Performances are also shown with other V_DD such as 1.0 and 1.8 Volts.

Keywords

CMOS analogue integrated circuits; circuit feedback; circuit simulation; current comparators; current-mode circuits; integrated circuit design; low-power electronics; -100 to 100 nA; -50 to 50 pA; 0.25 micron; 1.0 V; 1.5 V; 1.8 V; 3.6 ns; CMOS current comparator; current-mode circuits; high speed comparator; input current; low input current comparator; low voltage comparator; negative feedback; propagation delays; speed improvement; transformed voltage signal swing; transimpedance stage loop-gain; CMOS technology; Circuits; High power amplifiers; Inverters; Low voltage; MOSFETs; Maintenance engineering; Negative feedback; Propagation delay; Rail to rail outputs;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205593

Filename

1205593