Implementation of technology scaling on leakage reduction techniques using cadence tools with 45 nm technology

The impact of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) is evaluated by determining limits and benefits, in terms of the potential leakage reduction, performance penalty, and area and power overhead in 180nm, 90nm, and 45nm technologies. Cadence simulation results and estimations with various functional units and memory structures are presented to support a comprehensive analysis.