DocumentCode :
3534001
Title :
Area estimation and optimisation of FPGA routing fabrics
Author :
Smith, Alastair M. ; Constantinides, George A. ; Cheung, Peter Y K
Author_Institution :
Dept. of Electr. & Electron. Eng., Imperial Coll. London, London, UK
fYear :
2009
fDate :
Aug. 31 2009-Sept. 2 2009
Firstpage :
256
Lastpage :
261
Abstract :
This paper presents a methodology for estimating and optimising FPGA routing fabrics using high-level modelling and convex optimisation techniques. Experimental methods for exploring design spaces suffer from expensive computation time, which is exacerbated by increased dimensionality due to the larger number of architectural parameters. In this paper we build on previously published work to describe a model of FPGA routing area. This model is used in conjunction with a form of optimisation known as geometric programming, in order to analytically derive optimised FPGA architectural parameters, demonstrating the power and accuracy of model-based approaches in configurable architecture design. We show that routing parameters such as connection and switch box flexibilities can be architected to save around 6% of area instead of using traditional ldquorules of thumbrdquo.
Keywords :
convex programming; field programmable gate arrays; geometric programming; logic design; network routing; reconfigurable architectures; FPGA architectural parameter; FPGA routing fabrics; area estimation; convex optimisation technique; geometric programming; high-level modelling; Computer architecture; Design optimization; Equations; Fabrics; Field programmable gate arrays; Logic; Optimization methods; Routing; Space exploration; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on
Conference_Location :
Prague
ISSN :
1946-1488
Print_ISBN :
978-1-4244-3892-1
Electronic_ISBN :
1946-1488
Type :
conf
DOI :
10.1109/FPL.2009.5272298
Filename :
5272298
Link To Document :
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