Title :
VSPTIDR: A Novel Code for Test Compression of SoC
Author :
Cui, Xiaole ; Yin, Liang ; Hong, Jinxi ; Zuo, Renfu ; Cui, Xiaoxin ; Chen, Wei
Author_Institution :
Shenzhen Grad. Sch., Key Lab. of Integrated Microsyst., Peking Univ., Shenzhen
Abstract :
The bandwidth between automatic test equipment (ATE) and circuit under test is a bottleneck in the integrated circuit (IC) test. To reduce IC test time and cost, a novel variable shifting prefix-tail ID reverse (VSPTIDR) code for test stimulus data compression is designed in this paper. The coding rules and decoder are presented in detail. While the probability of Os in the test set is greater than 0.92, better compression ratio that acquire by VSPTIDR code contrasting with FDR code can be proved by theoretical analysis and experiments. And the on-chip area overhead of VSPTIDR decoder is about 15.75% less than FDR decoder.
Keywords :
automatic test equipment; integrated circuit testing; logic testing; system-on-chip; SoC; VSPTIDR; automatic test equipment; circuit under test; shifting prefix-tail ID reverse code; test stimulus data compression; Automatic test equipment; Automatic testing; Built-in self-test; Circuit testing; Costs; Data compression; Decoding; Integrated circuit testing; Tail; Test data compression;
Conference_Titel :
Testing and Diagnosis, 2009. ICTD 2009. IEEE Circuits and Systems International Conference on
Conference_Location :
Chengdu
Print_ISBN :
978-1-4244-2587-7
DOI :
10.1109/CAS-ICTD.2009.4960908
