• DocumentCode
    3534067
  • Title

    Cost trade-offs of various design for test techniques

  • Author

    Druckerman, Howard B. ; Kusko, Mary P. ; Pateras, Stephen ; Shephard, Philip G., III

  • fYear
    1994
  • fDate
    16-17 May 1994
  • Firstpage
    45
  • Abstract
    Test cost is becoming a major factor in today´s complex chip designs. One approach to lower test cost is to have the product test, or help test, itself. There are a wide variety of Design-for-Test techniques that have been developed for this purpose. A number of these techniques are evaluated against various related cost issues
  • Keywords
    Built-in self-test; Circuit testing; Clocks; Costs; Design for testability; Hardware; Latches; Logic testing; Shift registers; System testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Economics of Design, Test, and Manufacturing, 1994. Proceedings., Third International Conference on the
  • Conference_Location
    Austin, TX, USA
  • Print_ISBN
    0-8186-6595-5
  • Type

    conf

  • DOI
    10.1109/ICEDTM.1994.496091
  • Filename
    496091
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3534067