Test strategy selection for multi-chip systems

This paper describes an approach for selecting cost effective test strategies for multi-chip systems. The approach explores the test space that results from design options, component choice, and alternative test methods. Module-level test solutions are evaluated according to their impact on system cost and quality. The approach enhances test resources sharing between adjacent modules by determining the proper amount of DFT/BIST to include in every module. The large space of alternative solutions is reduced progressively to narrow the final optimization in a limited number of potential test strategies. The results for a sample MCM are presented