• DocumentCode
    3534197
  • Title

    RISPP: A run-time adaptive reconfigurable embedded processor

  • Author

    Bauer, Lars ; Shafique, Muhammad ; Henkel, Jörg

  • Author_Institution
    Dept. of Embedded Syst., Univ. of Kalsruhe, Kalsruhe, Germany
  • fYear
    2009
  • fDate
    Aug. 31 2009-Sept. 2 2009
  • Firstpage
    725
  • Lastpage
    726
  • Abstract
    Processors that deploy reconfigurable fabrics to implement application-specific accelerators on-demand obtained significant attention within the last decade. They trade-off the flexibility of general-purpose processors with the performance of application-specific circuits without tailoring the processor towards a specific application domain like application specific instruction set processors (ASIPs). However, even though they reconfigure parts of the hardware at run time, the decisions which accelerators shall be reconfigured at which time are typically determined at compile time. Therefore, it is conceptually not possible to react to dynamically changing situations like varying dynamic control flow (e.g. due to changed input data), changing task priorities / performance constraints, and changing availability of reconfigurable hardware (may be reassigned to another task). This work presents the novel rotating instruction set processing platform (RISPP) with its run-time system that enables dynamic adaptations in the above highlighted scenarios efficiently. Therefore, the presented approach is suitable for long-term as well as frequent adaptation requirements.
  • Keywords
    embedded systems; instruction sets; microprocessor chips; reconfigurable architectures; ASIP; RISPP processor; application specific instruction set processor; application-specific accelerator; dynamic control flow; general-purpose processor; rotating instruction set processing platform; run-time adaptive reconfigurable embedded processor; state-of-the-art reconfigurable architectures; Application specific processors; Availability; Embedded system; Fabrics; Flexible printed circuits; Frequency; Hardware; Prefetching; Reconfigurable architectures; Runtime;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on
  • Conference_Location
    Prague
  • ISSN
    1946-1488
  • Print_ISBN
    978-1-4244-3892-1
  • Electronic_ISBN
    1946-1488
  • Type

    conf

  • DOI
    10.1109/FPL.2009.5272323
  • Filename
    5272323