Simultaneous partitioning, scheduling and allocation for synthesis of multi-chip module architectures

We present a simultaneous partitioning, scheduling and allocation technique for the synthesis of multi-chip module architectures. It is based on the stochastic evolution heuristic, which is an effective heuristic for solving several combinatorial optimization problems. Before the actual partitioning is performed, supernodes are created based on the scheduling/allocation constraints which in turn reduces the search space for the partitioner. We formulate the partitioning problem as an extension to the network-bisectioning problem for which the stochastic evolution heuristic has been shown to provide better results than the simulated annealing technique. Scheduling/allocation and pin sharing are also performed simultaneously with partitioning to estimate the area and pincount requirements for each of the partitions. Efficient partitions are obtained for some of the digital signal processing applications in reasonable CPU time