A novel adder cell for leakage current reduction in nanoscale VLSI circuits

This paper proposes a high-speed adder cell using a new design style called "bridge". The bridge design style offers more regularity and higher density than conventional CMOS design style, by using some transistors, named bridge transistors. The new approach is known as "Sleepy Keeper". This report first introduces previous approaches to reduce leakage power consumption and then explains the methodology and findings regarding the sleepy keeper approach. Until recent years, dynamic power dissipation contributed the most to the chip\´s total power dissipation in CMOS digital circuits thus much attention was given to reduce this dynamic power. But as technology advances into the sub-100 nm regime, leakage power dissipation, which is a static power, increases at a much faster rate than dynamic power and it is expected to dominate the chips\´ total power dissipation. HSPICE is the circuit simulator used and the technology being used for simulations is Predictive Technology Models (PTM). Based on experiments with a 4-bit adder circuit, sleepy keeper approach achieves up to 49% less delay and 49% less area than the sleepy stack approach. Unfortunately, sleepy keeper causes additional dynamic power consumption, approximately 15% more than the base case (no sleep transistors used at all).