Title :
Compact FPGA implementation of Camellia
Author :
Yalla, Panasayya ; Kaps, Jens-Peter
Author_Institution :
Volgenau Sch. of IT&E, George Mason Univ., Fairfax, VA, USA
fDate :
Aug. 31 2009-Sept. 2 2009
Abstract :
We present the smallest FPGA implementation of Camellia for 128-bit key length to date. This architecture was designed for low area and low power applications. Through specific optimizations such as shift registers for storing and scheduling key, distributed RAM for storing data, we achieved compact implementation using only 318 slices at a throughput of 18.41 Mbps on the smallest Xilinx Spartan-3 XC3S50-5 device.
Keywords :
cryptography; field programmable gate arrays; low-power electronics; random-access storage; shift registers; 318 slices; Camellia; Xilinx Spartan-3 XC3S50-5 device; bit rate 18.41 Mbit/s; compact FPGA implementation; distributed RAM; key scheduling; low power application; Cryptography; Field programmable gate arrays; Logic; Multiplexing; Random access memory; Read-write memory; Scheduling; Shift registers; Table lookup; Throughput;
Conference_Titel :
Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on
Conference_Location :
Prague
Print_ISBN :
978-1-4244-3892-1
Electronic_ISBN :
1946-1488
DOI :
10.1109/FPL.2009.5272349
