A new CMOS charge pump for low-voltage (1V) high-speed PLL applications

Author

Baki, Rola A. ; El-Gamal, Mourad N.

Author_Institution

Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada

Volume

1

fYear

2003

fDate

25-28 May 2003

Abstract

This paper proposes a new charge pump structure for phase locked loop (PLL) applications. The circuit is optimized to minimize the amount of glitches in the output current. It is designed in a standard CMOS 0.18μm technology, and it operates from a 1V power supply. The output voltage has a relatively wide range, from 100mV up to 900mV, and does not exhibit any spurious jump phenomenon. Simulation results in HSPICE show the capability of high-frequency operation (500MHz), with very low-power consumption (60μW).

Keywords

CMOS integrated circuits; SPICE; circuit simulation; high-speed integrated circuits; low-power electronics; phase locked loops; 0.18 micron; 1 V; 100 to 900 mV; 500 MHz; 60 muW; CMOS charge pump; HSPICE; glitches; high-frequency operation; high-speed PLL applications; low-power consumption; output current; output voltage; spurious jump phenomenon; Application software; CMOS technology; Charge pumps; Circuits; Phase frequency detector; Phase locked loops; Power supplies; Switches; Voltage; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205649

Filename

1205649