Title :
Exploiting synchronous placement for asynchronous circuits onto commercial FPGAs
Author :
Tranchero, Maurizio ; Reyneri, Leonardo M.
Author_Institution :
Dipt. di Elettron., Politec. di Torino, Torino, Italy
fDate :
Aug. 31 2009-Sept. 2 2009
Abstract :
This paper describes an approach to the placement of self-timed circuits onto commercial FPGAs, using only conventional synchronous tools available on the market. Different parts of the design are constrained in order to maintain the timing relationship required for guaranteeing the correct circuit functionality and to keep the wiring influence on system delays bounded and fixed across the different iterations. This work is part of the extension to the CodeSimulink co-design environment we made in order to allow the synthesis of asynchronous circuits from Simulink specifications.
Keywords :
asynchronous circuits; field programmable gate arrays; logic design; CodeSimulink codesign; asynchronous circuit; commercial FPGA; self-timed circuit; Asynchronous circuits; Energy consumption; Field programmable gate arrays; Hardware; Mathematical model; Protocols; Routing; Software libraries; Time to market; Timing;
Conference_Titel :
Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on
Conference_Location :
Prague
Print_ISBN :
978-1-4244-3892-1
Electronic_ISBN :
1946-1488
DOI :
10.1109/FPL.2009.5272378