FPGA-implementation of Time-Multiplexed Multiple Constant Multiplication based on carry-save arithmetic

This paper proposes a method to implement time-multiplexed multiple constant multiplication (T-MMCM) based on carry-save adders on FPGA devices. Some basic cells have been defined. These cells are efficiently mapped on the FPGA devices and allow the designer to built T-MMCM circuits based on a tree topology. The performance of the proposed method has been validated by means of two designs: an n-point FFT butterfly with n=64, 128 and 256, and a 2-D DCT. Both designs have been implemented on a Virtex-5 device. The results show that the proposed method improves the throughput (up to 50%) and reduces the area in many cases compared to the implementation based on carry-propagate adders.