Analysis of timing jitter in ring oscillators due to power supply noise

Author

Pialis, T. ; Phang, K.

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

Volume

1

fYear

2003

fDate

25-28 May 2003

Abstract

This paper presents a time-domain method for estimating the jitter in ring oscillators that is due to power supply noise. The method is used to analyze and compare the RMS cycle-to-cycle jitter of ring oscillators constructed from three possible delay elements: a CMOS digital inverter, a differential pair, and a current steering logic (CSL) inverter. Spice simulations verify the analysis method, and the results indicate that both the differential pair and CSL inverter provide superior supply noise immunity to the CMOS digital inverter.

Keywords

CMOS digital integrated circuits; integrated circuit noise; network analysis; oscillators; timing jitter; voltage-controlled oscillators; CMOS digital inverter; CSL inverter; RMS cycle-to-cycle jitter; current steering logic inverter; delay elements; differential pair; power supply noise; ring oscillators; ring-based VCO; supply noise immunity; time-domain method; Delay effects; Delay estimation; Inverters; Phase noise; Power supplies; Ring oscillators; Threshold voltage; Time domain analysis; Timing jitter; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205656

Filename

1205656