Off-line placement of hardware tasks on FPGA

The new tendencies in designing real-time systems indicate that the future applications will be built on reconfigurable hardware devices. These applications require high performance and reasonable flexibility towards user and environment needs. To fulfill these application requirements, the density of heterogeneous resources evolves within these devices. Hence, the complexity of these devices leads to the search of efficient mechanisms to manage hardware resources. The proposed placement methods suffer from issues of fragmentation, tasks rejection, and overheads. This paper focuses on an off-line flow of hardware tasks´ classification that aims at the optimized use of the resources and targets all above mentioned issues.