DocumentCode :
3534875
Title :
Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors
Author :
Sano, Toru ; Saito, Yoshiki ; Kato, Masaru ; Amano, Hideharu
Author_Institution :
Dept. of Inf. & Comput. Sci., Keio Univ., Yokohama, Japan
fYear :
2009
fDate :
Aug. 31 2009-Sept. 2 2009
Firstpage :
530
Lastpage :
533
Abstract :
Based on the power consumption analysis of a real dynamically reconfigurable processor array (DRPA) prototype MuCCRA-3, it appears that the key of power saving is keeping the datapath on the processing element (PE) array as possible. Fine grain partial reconfiguration (FGPR) is a simple technique to minimize the change of configuration code in a hardware context switching. In FGPR, a configuration code is divided into several components and only the configuration data for the required components are changed. Evaluation results demonstrate that about 15% of the power consumption is reduced with only 0.7% hardware overhead. The total amount of configuration data and its loading time can be also reduced by 37% in average.
Keywords :
low-power electronics; microprocessor chips; multiprocessing systems; reconfigurable architectures; system-on-chip; DRPA; MuCCRA-3 prototype; configuration code; dynamically reconfigurable processor array; energy saving; fine grain partial reconfiguration; hardware context switching; power consumption analysis; processing element array; system-on-chip; Computer science; Energy consumption; Engines; Games; Hardware; Information analysis; National electric code; Prototypes; Switches; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on
Conference_Location :
Prague
ISSN :
1946-1488
Print_ISBN :
978-1-4244-3892-1
Electronic_ISBN :
1946-1488
Type :
conf
DOI :
10.1109/FPL.2009.5272435
Filename :
5272435
Link To Document :
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