A nanoscale vertical-tunneling FET

Simulates silicon-based FETs having a radically new architecture, one which could eventually permit scaling of overall device dimensions to 500A or less while simultaneously eliminating the large-area contacts and isolation required in conventional MOSFETs. This approach assumes that it will be possible to selectively pattern epitaxial films into the silicon substrate at nanometer resolution, and to subsequently overgrow these patterns with heterolayer structures. Selective epitaxial metallization of this type can potentially provide the basis for a wide variety of nanoscale devices in which transport occurs through appropriately designed heterolayers in the vertical (growth) direction under control of a gate electrode.