A method to reduce power consumption in pipelined A/D converters

This paper describes a method to reduce the supply voltage for the MDACs (multiplying digital to analog converter) in pipelined or algorithmic A/D converters that results in lower power consumption. The technique is based on using digital code correction to limit the output voltage swing of MDACs to almost half. Since the input voltage range, the reference voltage and V_LSB remain unchanged, the size of the capacitors dictated by thermal noise and matching considerations is conserved. The analysis presented shows that the settling error improves and that the performance degradation coming from lower supply voltage is eliminated. The method is appropriate for scaling CMOS mixed-signal designs where low voltage and low power consumption are important requirements.