A 1.8-v high-speed 13-bit pipelined analog to digital converter for digital IF applications

A 1.8-v 13-bit 25MS/S pipelined analog-to-digital (A/D) converter was designed and simulated using 0.18um CMOS technology. The proposed new high speed low power class AB opamp makes it possible to achieve requirements of 13-bit resolution and settling in 12ns within 0.01% accuracy. An optimum architecture for noise and power consideration is also selected to reduce power. Total Power dissipation is about 82 mw from a single 1.8v supply, where INL and DNL are 0.7 LSB and 0.6 LSB respectively. SNDR of 75.5 dB is achieved.