DocumentCode
3535236
Title
An analytical model relating FPGA architecture and place and route runtime
Author
Chin, Scott Y L ; Wilton, Steven J E
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of British Columbia, Vancouver, BC, Canada
fYear
2009
fDate
Aug. 31 2009-Sept. 2 2009
Firstpage
146
Lastpage
153
Abstract
This paper presents an analytical model that relates the architectural parameters of an FPGA to the place-and-route runtimes of the FPGA CAD tools. We consider both a simulated annealing based placement algorithm employing a bounding box wirelength cost function, and a negotiation based A* router. We also show an example application of the model in early architecture evaluation.
Keywords
field programmable gate arrays; logic CAD; network routing; simulated annealing; FPGA CAD tool; analytical model relating FPGA architecture; bounding box wirelength cost function; place runtime; route runtime; simulated annealing based placement algorithm; Analytical models; Circuits; Computational modeling; Design automation; Field programmable gate arrays; Logic; Routing; Runtime; Scalability; Simulated annealing;
fLanguage
English
Publisher
ieee
Conference_Titel
Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on
Conference_Location
Prague
ISSN
1946-1488
Print_ISBN
978-1-4244-3892-1
Electronic_ISBN
1946-1488
Type
conf
DOI
10.1109/FPL.2009.5272519
Filename
5272519
Link To Document