Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation

Author

Claus, Christopher ; Huitl, Robert ; Rausch, Joachim ; Stechele, Walter

Author_Institution

Inst. for Integrated Syst., Tech. Univ. Munchen, Munich, Germany

fYear

2009

fDate

Aug. 31 2009-Sept. 2 2009

Firstpage

138

Lastpage

145

Abstract

In many embedded systems for video surveillance distinctive features are used for the detection of objects. In this contribution a real-time FPGA implementation of a feature detector, namely the SUSAN algorithm is described. As the original SUSAN algorithm performs poorly on non-synthetic images a significant quality improvement of this algorithm is presented. The hardware accelerator outperforms a comparable software version running on an Intel Core2Duo E8400 core at 3.00 GHz and delivers almost the same execution time compared to an implementation of the Harris corner detector running on an Nvidia GeForce 8800 GTX GPU.

Keywords

edge detection; embedded systems; feature extraction; field programmable gate arrays; object detection; video surveillance; Harris corner detector; Intel Core2Duo E8400 core; Nvidia GeForce 8800 GTX GPU; SUSAN corner detection algorithm; embedded system; feature detector; frequency 3 GHz; hardware accelerator; high-speed real-time FPGA implementation; nonsynthetic image; object detection; quality improvement; software version; video surveillance feature; Clocks; Detection algorithms; Detectors; Embedded system; Field programmable gate arrays; Frequency; Hardware; Image edge detection; Object detection; Pixel;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on

Conference_Location

Prague

ISSN

1946-1488

Print_ISBN

978-1-4244-3892-1

Electronic_ISBN

1946-1488

Type

conf

DOI

10.1109/FPL.2009.5272524

Filename

5272524