BP decimation filter for IF-sampling merged with BP ΣΔ-modulator

An analog discrete-time bandpass (BP) decimation filter is presented, which enables a lower clock frequency of the BP ΣΔ-modulator without tightening clock jitter and IF filtering specifications. The designed decimator is combined with a 2b/4b 4th-order double-sampling BP ΣΔ-modulator targeted for an IF-receiver. The circuit can be used in an IF-receiver to combine frequency down-conversion with analog to digital conversion by directly sampling an input signal from an intermediate frequency of 90 MHz to a digital intermediate frequency of 10 MHz. Simulated SNR is 84 dB for a 270 kHz (GSM) bandwidth. The estimated power dissipation with a 0.35 μm CMOS technology is 16 mW at 3.0 V.