Efficient design and FPGA implementation of JPEG encoder using verilog HDL

The JPEG encoder is a major component in JPEG standard which is used in image compression. It involves a complex sub-block discrete cosine transform (DCT), along with other quantization, zigzag and Entropy coding blocks. In this paper Verilog design and hardware implementation of pipelined 2-D DCT along with zigzag, quantization and variable length coding is described. 2-D DCT is computed by combining two 1-D DCT that connected by a transpose buffer. The architecture uses 4059 slices, 6885 LUT, 58 I/Os of Xilinx Spartan-3 XC3S1500 FPGA and works at an operating frequency of 65.55 MHz. The delay of processing each 8*8 block in an image is also evaluated to be 1.47micro seconds.