Functional testing of array processors

The authors present a functional testing method applicable to VLSI arrays. A system with single-instruction multiple-data processing is assumed, and computing elements are connected by a regular interconnection network. A fault model for the array is presented. Faults are defined at a functional level and allow a systematic test generation procedure to be derived. This procedure is independent of array implementation details and still remains a SIMD characterization. Testing is performed by sequences of instructions defined by using two ordering criteria. The first criterion establishes the external observability and controllability of the instructions. The second criterion uses instruction cardinality as metric for evaluation of instruction complexity. Algorithms and procedures for a correct execution of functional testing are presented. An example of the application of the proposed technique to an existing parallel scheme is described. The criteria for structuring the test procedure lead to an optimization of fault coverage and a reduction of ambiguity