ESD protection for SOI technology using an under-the-box (substrate) diode structure

Author

Salman, Akram ; Pelella, Mario ; Beebe, Stephen ; Subba, Niraj

Author_Institution

Adv. Micro Devices, Sunnyvale, CA, USA

fYear

2004

fDate

19-23 Sept. 2004

Firstpage

1

Lastpage

7

Abstract

In this paper we will present a new integrated SOI substrate diode structure for ESD protection of SOI I/O circuits that is built under the buried oxide of the SOI wafer using a standard CMOS process. We will show that the protection level can reach four times what is achieved by the standard-lateral SOI diode structure. We will also show device and process simulation results to understand the self-heating effect of both standard-SOI and substrate diodes, as well as how to optimize the structure using a deep N-well implant.

Keywords

CMOS integrated circuits; electrostatic discharge; silicon-on-insulator; ESD protection; N-well implant; SOI I-O circuits; SOI substrate diode structure; SOI wafer; electrostatic discharge protection; standard CMOS process; under-the-box diode structure; CMOS process; CMOS technology; Circuits; Diodes; Electrostatic discharge; Implants; Microprocessors; Protection; Substrates; Thermal conductivity;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium, 2004. EOS/ESD '04.

Conference_Location

Grapevine, TX

Print_ISBN

978-1-5853-7063-4

Electronic_ISBN

978-1-5853-7063-4

Type

conf

DOI

10.1109/EOSESD.2004.5272603

Filename

5272603