DocumentCode :
3535889
Title :
CDM failure modes in a 130nm ASIC technology
Author :
Brennan, Ciaran J. ; Sloan, Jeffrey ; Picozzi, David
Author_Institution :
IBM Microelectron., Essex Junction, VT, USA
fYear :
2004
fDate :
19-23 Sept. 2004
Firstpage :
1
Lastpage :
5
Abstract :
CDM failures in I/O cells in a 130 nm CMOS ASIC technology are studied. Most failures occurred in internal circuits that were not connected to chip pads. The failures correlate to the I/O power supply network resistance at the I/O cells. Failure modes include gate oxide ruptures on internal nodes driven by active circuits.
Keywords :
CMOS integrated circuits; application specific integrated circuits; failure analysis; ASIC technology; CDM failure modes; I/O cells; I/O power supply network resistance; active circuits; chip pads; gate oxide ruptures; size 130 nm; Application specific integrated circuits; CMOS technology; Diodes; Electrostatic discharge; FETs; Impedance; Libraries; Power supplies; Protection; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium, 2004. EOS/ESD '04.
Conference_Location :
Grapevine, TX
Print_ISBN :
978-1-5853-7063-4
Electronic_ISBN :
978-1-5853-7063-4
Type :
conf
DOI :
10.1109/EOSESD.2004.5272610
Filename :
5272610
Link To Document :
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