DocumentCode :
3536035
Title :
A low power implementation of PSK modems in FPGA with reconfigurable filter and digital NCO using PR for SDR and CR applications
Author :
Arun Kumar, K.A.
Author_Institution :
Centre for Dev. of Adv. Comput., Trivandrum, India
fYear :
2012
fDate :
18-20 Dec. 2012
Firstpage :
192
Lastpage :
197
Abstract :
The role of FPGAs in software defined Radios (SDR) and Cognitive radios (CR) are very significant. These radios have to load different waveform depending on their requirements which may use different source coding, channel coding and modulation schemes. The user has to load large bit files even for small changes in the waveforms. In SDRs and CRs the configuration time and power consumption plays significant role: for example, a virtex-7 FPGA takes 500ms to complete configuration. If the waveforms design is made Partially Reconfigurable then the configuration time and the Hardware usage can be saved. The Objective of this work is to make the Modulation and demodulation (PSK) Schemes partially reconfigurable. The paper describes the Design and Implementation of Phase Shift keying (PSK) Modulation and demodulation in FPGA using Partial Re-configuration (PR). This work involves the Design and implementation of BPSK, QPSK, 8-PSK and 16-PSK modulation and demodulation schemes in FPGA. There is a RRC Filter and a Digital Up converter followed by the modulators and there is a Digital Down converter in the demodulator section. The user can swap between different modulation and demodulation schemes during runtime by configuring a control register in FPGA. The Implementation of these PSKs shares a common hardware, which is the Static Part and there is a Dynamic part too. In the PR, the user has to load the bit stream for the Dynamic part only, and not the entire bit stream. This will be smaller in size compared to the large bit file. The Up/Down converter design consists of two DDS modules and the demodulator part consists of a four DDS modules, which forms the static part of the design. By designing the entire waveform using partial Reconfiguration, the waveform can be made as part of the Platform realized. Here using Partial reconfiguration the Distributed Arithmetic (DA) architecture the power consumption is very much reduced.
Keywords :
cognitive radio; convertors; demodulation; digital arithmetic; field programmable gate arrays; filters; integrated circuit design; phase shift keying; reconfigurable architectures; software radio; system-on-chip; telecommunication computing; 16-PSK de modulation scheme; 16-PSK modulation scheme; 8-PSK demodulation scheme; 8-PSK modulation schemes; BPSK demodulation scheme; BPSK modulation scheme; CR applications; DDS modules; PSK modems; QPSK demodulation scheme; QPSK modulation schemes; RRC filter; SDR applications; SoC design technique; Virtex-7 FPGA; channel coding scheme; cognitive radios; configuration time; control register; demodulator section; digital NCO; digital down converter; digital up converter; distributed arithmetic architecture; field programmable gate array; low power implementation; modulation scheme; partial reconfiguration; phase shift keying; power consumption; reconfigurable filter; software defined radios; source coding scheme; up-down converter design; Demodulation; Field programmable gate arrays; Generators; Mathematical model; Phase shift keying; Switches; CR; DDS; FPGA; Partial Reconfiguration; RTL; SDR; SoC;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Green Technologies (ICGT), 2012 International Conference on
Conference_Location :
Trivandrum
Print_ISBN :
978-1-4673-2635-3
Type :
conf
DOI :
10.1109/ICGT.2012.6477971
Filename :
6477971
Link To Document :
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