Design and implementation of a reconfigurable FIR filter

Author

Chen, Kuan-Hung ; Chiueh, Tzi-Dar

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

4

fYear

2003

fDate

25-28 May 2003

Abstract

Finite impulse response (FIR) filters are very important blocks in digital communication systems. Many efforts have been made to improve the filter performance, e.g., less hardware and higher speed. In addition, software radio has recently gained much attention due to the need for integrated and reconfigurable communication systems. To this end, reconfigurability has become an important issue for the future filter design. In this paper, we present a digit-reconfigurable FIR filter architecture with the finest granularity. The proposed architecture is implemented in a single-poly quadruple-metal 0.35-μm CMOS technology. Measurement results show that the fabricated chip consumes 16.5 mW of power when operating at 86 MHz under 2.5 V.

Keywords

CMOS digital integrated circuits; FIR filters; digital filters; reconfigurable architectures; software radio; 0.35 micron; 16.5 mW; 2.5 V; 86 MHz; digit-reconfigurable architecture; digital communication systems; filter design; filter performance; granularity; reconfigurable FIR filter; single-poly quadruple-metal CMOS; software radio; CMOS technology; Communication system software; Computer architecture; Digital communication; Digital filters; Filtering; Finite impulse response filter; Hardware; Matched filters; Pulse shaping methods;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205809

Filename

1205809