Pass-transistor logic and its sub-Vdd voltage-swing behaviours in low-voltage circuit design

Author

Cheung, T.S. ; Wong, H. ; Cheng, Y.C.

Author_Institution

Dept. of Electron. Eng., Tokyo Univ., Japan

fYear

1995

fDate

6-10 Nov 1995

Firstpage

307

Lastpage

310

Abstract

Internal signal propagation with voltage swing less than the supply voltage have been proposed through various architecture or structures. Reduced supply voltage in digital and analog circuits is considered to be one of the best methods for achieving real low power dissipation circuits. In this paper, pass-transistor logic with suppressed internal voltage-swing is investigated and analyzed. A proposal on a reduced swing 14-bit parity generator and carry generation blocks of a parallel full adder are also given. In addition, optimization on propagation delay can be achieved by proper tapering of the dimension of the transistors

Keywords

CMOS logic circuits; adders; delays; logic design; timing; carry generation block; internal signal propagation; internal voltage-swing suppression; low power dissipation circuits; low-voltage circuit design; optimization; parallel full adder; parity generator; pass-transistor logic; propagation delay; sub-Vdd voltage-swing behaviour; CMOS technology; Capacitance; Circuit synthesis; Delay effects; Integrated circuit technology; Logic circuits; Logic design; Power dissipation; Propagation delay; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on

Print_ISBN

0-7803-2624-5

Type

conf

DOI

10.1109/TENCON.1995.496401

Filename

496401