Title :
Optimization of Low Power 7T SRAM Cell in 45nm Technology
Author :
Jain, Anie ; Sharma, Shantanu
Author_Institution :
Inst. of Technol. & Manage., Gwalior, India
Abstract :
In this paper a low power SRAM cell is proposed. In the proposed SRAM topology, additional circuitry has been added to a standard 6T-SRAM cell to improve the performance. A seven transistor (7T) cell at a 45nm feature size in CMOS is proposed to accomplish improvements in stability, power dissipation and performance compared with previous designs for low-power memory operation. By optimizing size and employing the proposed write circuitry scheme, a saving of 45% in power consumption is achieved in memory array operation compared with a conventional 6T SRAM based design. The impact of process variations is investigated in detail, and the CADENCE simulation shows that the 7T SRAM cell has an excellent tolerance to process variations.
Keywords :
CMOS memory circuits; SRAM chips; integrated circuit design; 6T SRAM cell based design; CADENCE simulation; CMOS technology; SRAM topology; low power 7T SRAM cell optimization; low-power memory operation; power consumption; power dissipation; seven transistor SRAM cell; size 45 nm; Arrays; CMOS integrated circuits; Leakage current; Power demand; Random access memory; Stability analysis; Transistors; 7T SRAM; Conventional SRAM; Leakage Current; Low Power; Output waveform;
Conference_Titel :
Advanced Computing & Communication Technologies (ACCT), 2012 Second International Conference on
Conference_Location :
Rohtak, Haryana
Print_ISBN :
978-1-4673-0471-9
DOI :
10.1109/ACCT.2012.81
