DocumentCode
3536762
Title
Implementation of synthesized digital systems with VHDL
Author
Ng, L.S. ; Jong, C.C.
Author_Institution
Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore
fYear
1995
fDate
6-10 Nov 1995
Firstpage
339
Lastpage
342
Abstract
This paper presents a software system for implementing synthesized digital designs using VHDL so that the designs can be accepted by existing CAD systems to achieve low-level verification such as delay analysis and logic simulation as well as layout realization in various technologies
Keywords
circuit layout CAD; data flow graphs; finite state machines; hardware description languages; high level synthesis; CAD systems; VHDL; delay analysis; layout realization; logic simulation; low-level verification; software system; synthesized digital systems; Analytical models; Control system synthesis; Delay; Design automation; Digital systems; Flow graphs; Hardware design languages; High level synthesis; Logic design; Software systems;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on
Print_ISBN
0-7803-2624-5
Type
conf
DOI
10.1109/TENCON.1995.496409
Filename
496409
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