Title :
Testing and Formal Verification of Decoder Circuit
Author :
Bhuria, Indu ; Inaniya, Pawan ; Kaler, Pramod
Author_Institution :
Deptt. Of Electron. & Commun, Gov. Eng. Coll., Bikaner, India
Abstract :
Testing of 2-to-4 decoder circuit are been done using tetraMAX. It is observed that 54 possible stuck-at faults can be there in the 2-to-4 decoder circuit, tetraMAX ATPG can provide test coverage of 100 % Using design compiler. db file is generated which is used for functional verification of the design with respect to RTL design. Compare points are shown by cone views of the design.
Keywords :
automatic test pattern generation; circuit testing; combinational circuits; decoding; electronic engineering computing; fault diagnosis; logic design; logic testing; 2-to-4 decoder circuit formal verification; 2-to-4 decoder circuit testing; RTL design; combinational type logic circuit; stuck-at fault; tetraMAX ATPG; Automatic test pattern generation; Circuit faults; Decoding; Flip-flops; Formal verification; Hardware design languages; Design Analyzer; Formality; TetraMax;
Conference_Titel :
Advanced Computing & Communication Technologies (ACCT), 2012 Second International Conference on
Conference_Location :
Rohtak, Haryana
Print_ISBN :
978-1-4673-0471-9
DOI :
10.1109/ACCT.2012.111
