Alternative Direct Digital Frequency Synthesizer architectures with reduced memory size

The overall operation of a Direct Digital Frequency Synthesizer (DDFS) is based on a look up table method, which performs functional mapping from phase to sine amplitude. The spectral purity of the conventional DDFS is determined by the resolution of the values stored in the sine table ROM. However, large ROM storage means higher power consumption, lower reliability, lower speed and increased costs. The novel design and implementation of a DDFS, with reduced memory size, is introduced. Using new technique, the resulting architecture can be realized by smaller number of gates (i.e. less hardware complexity) than existing ones. Describing the proposed architecture, with the hardware description language VHDL, we can generate plethora of alternative realizations in terms of the number of inputs and output bits, the memory size, the number of gates, the memory segmentation parameters, and the spectral purity. In other words, the designer can perform extensive architecture exploration to reach his/her optimal solution.