Title :
An implementation of branch target buffer for high performance applications
Author :
Sonh, Seung Il ; Hoon Mo Yang ; Moon Key Lee
Author_Institution :
Dept. of Electron. Eng., Yonsei Univ., Seoul, South Korea
Abstract :
Efficient executions of branch instructions are one of the most important issues in implementing high performance microprocessors. Branching instructions are above 20% of total instruction in most programs. BTB (Branch Target Buffer) enhances the speed of branch instruction execution by predicting the branch path, including currently executed branch instruction address, prediction information, and target address. The BTB is designed as a 4-way set associative organization with 256 branch entries. Pseudo-LRU algorithm is used for replacement of lines instead of ordinary LRU algorithm. Also IP(Instruction Pointer) chain is designed for verifying the BTB
Keywords :
buffer circuits; instruction sets; interrupts; microprocessor chips; parallel architectures; pipeline processing; BTB; branch instruction execution; branch path; branch target buffer; high performance microprocessors; instruction pointer chain; prediction information; pseudo-LRU algorithm; set associative organization; target address; Clocks; Computer aided instruction; Decoding; Delay; Microprocessors; Moon; Parallel processing; Pipelines; Prefetching; Throughput;
Conference_Titel :
Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on
Print_ISBN :
0-7803-2624-5
DOI :
10.1109/TENCON.1995.496448
