VLSI design of turbo decoder for integrated communication system-on-chip applications

Author

Fang, Wai-Chi ; Sethuram, Ashwin ; Belevi, Kemal

Author_Institution

Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA

Volume

2

fYear

2003

fDate

25-28 May 2003

Abstract

A high-throughput low-power turbo decoder core has been developed for integrated communication system applications such as Digital Video Broadcast (DVB), satellite communications, wireless LAN, digital TV, cable modem, and xDSL systems. The turbo decoder is based on convolutional constituent codes, which outperform all other Forward Error Correction (FEC) techniques. This turbo decoder core is parameterizable and can be modified easily to fit any size for advanced communication system-on-chip products. The turbo decoder core provides FEC of up to 15 Mbit/s on a 0.13-micron CMOS FPGA prototyping chip at a power of 0.1 watt.

Keywords

CMOS integrated circuits; VLSI; decoding; digital communication; field programmable gate arrays; forward error correction; low-power electronics; system-on-chip; turbo codes; 0.1 W; 0.13 micron; 15 Mbit/s; CMOS FPGA prototype chip; FEC technique; VLSI design; cable modem; communication system-on-chip applications; convolutional constituent codes; digital TV; digital video broadcast; high-throughput turbo decoder; integrated communication SoC applications; low-power turbo decoder core; satellite communications; wireless LAN; xDSL systems; Cable TV; Communication cables; Decoding; Digital TV; Digital video broadcasting; Forward error correction; Satellite communication; System-on-a-chip; Very large scale integration; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205907

Filename

1205907