Title :
A 10Gb/s CDR with a half-rate bang-bang phase detector
Author :
Ramezani, Mehrdad ; Andre, C. ; Salama, T.
Author_Institution :
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Abstract :
A 10Gb/s PLL-based Clock and Data Recovery (CDR) circuit, with a half-rate bang-bang phase detector, is implemented using a 0.13μm CMOS technology. The clock frequency is 5GHz, generated using a fully differential four-stage VCO. The loop filter is implemented on chip. The design meets the requirements of the local area network (LAN). applications. The total power dissipation of the CDR is less than 150mW.
Keywords :
CMOS integrated circuits; mixed analogue-digital integrated circuits; phase detectors; phase locked loops; synchronisation; voltage-controlled oscillators; 0.13 micron; 10 Gbit/s; 150 mW; 5 GHz; CDR; CMOS; PLL-based Clock and Data Recovery circuit; fully differential four-stage VCO; half-rate bang-bang phase detector; local area network; total power dissipation; CMOS technology; Circuits; Clocks; Detectors; Filters; Frequency; Local area networks; Phase detection; Power dissipation; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1205927
