Title :
Scalable giga-pixels/s binary image morphological operations
Author :
Ongwattanakul, Songpol ; Chewputtanagul, Phaisit ; Jackson, David I. ; Ricks, Kenneth G.
Author_Institution :
Dept. of Electr. & Comput. Eng., Alabama Univ., Tuscaloosa, AL, USA
Abstract :
Binary morphological operations are a building block in many computer vision applications. Several iterative morphological operations are commonly performed for image analysis resulting in a significant computational load on the processing unit, especially in a real-time computer vision system. Custom designed hardware can exploit the parallelism exhibited in binary image morphological operations. In this paper, we describe a scalable parallel Binary Morphological Unit (spBMU) which can produce 2×8-pixel (2 rows × 8 columns) outputs from one of fifteen primitive morphological operations based on a 30 mask. Multiple spBMU can be linked to achieve higher parallel performance. Operations include Sobel edge detection, dilation, erosion, Laplacian, and edge thinning. Implementation on an Altera CPLD has shown a sustained performance up to 720 million output pixels per second per chip at 45 MHz. Eight spBMUs, yielding 5.76 Giga-pixels/s, can be implemented with relatively small modification to the memory structure. The spBMU architecture and details of implementation are presented.
Keywords :
application specific integrated circuits; computer vision; edge detection; image thinning; mathematical morphology; programmable logic devices; 45 MHz; Altera CPLD; Sobel edge detection; binary morphological operations; computer vision applications; custom designed hardware; dilation; edge thinning; erosion; image analysis; iterative morphological operations; memory structure modification; parallel performance; parallelism; programmable logic; real-time computer vision; scalable giga-pixels/s binary image morphological operations; scalable parallel binary morphological unit; Application software; Computer vision; Hardware; Image edge detection; Image processing; Laplace equations; Morphological operations; Parallel processing; Programmable logic arrays; Real time systems;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1206005