An FPGA implementation of shift converter block technique on FIFO for UART

Author

Jusoh, Nurul Fatihah ; Ibrahim, Azlina ; Haron, Muhamad Adib ; Sulaiman, Fuziah

Author_Institution

Fac. of Electr. Eng., Univ. Teknol. MARA, Shah Alam, Malaysia

fYear

2011

fDate

12-14 Dec. 2011

Firstpage

320

Lastpage

324

Abstract

To meet the standard modern system wireless communication demands, the paper represents the implementation of bidirectional shift converter technique with FIFO circuit block and UART (Universal Asynchronous Receiver Transmitter) circuit block through FPGA device using Verilog HDL language to be applied in embedded system converter RS232 to USB (Universal Serial Bus). Utilizing the ModelSim-Altera, RTL model of the shift converter was developed and synthesized then stimulated using TimeQuest Timing Analyzer to observe its functionality.

Keywords

convertors; data communication equipment; field programmable gate arrays; hardware description languages; peripheral interfaces; FIFO circuit block; FPGA; RS232-USB converter; TimeQuest timing analyzer; UART; Verilog HDL language; bidirectional shift converter technique; embedded system converter; shift converter block technique; universal asynchronous receiver transmitter; universal serial bus; Analytical models; Clocks; Engines; Field programmable gate arrays; Hardware design languages; Protocols; Registers; FIFO; FPGA; Shift Converter; UART;

fLanguage

English

Publisher

ieee

Conference_Titel

RF and Microwave Conference (RFM), 2011 IEEE International

Conference_Location

Seremban, Negeri Sembilan

Print_ISBN

978-1-4577-1628-7

Type

conf

DOI

10.1109/RFM.2011.6168758

Filename

6168758