Performance-oriented placement and routing for field-programmable gate arrays

Author

Alexander, Michael J. ; Cohoon, James P. ; Ganley, Joseph L. ; Robins, Gabriel

Author_Institution

Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA

fYear

1995

fDate

18-22 Sep 1995

Firstpage

80

Lastpage

85

Abstract

This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graph-based strategy for detailed routing, our tool optimizes source-sink pathlengths, channel width and total wire-length. Our results compare favorably with other FPGA layout tools, as measured by the maximum channel width required to place and route a number of industrial benchmarks

Keywords

circuit layout CAD; field programmable gate arrays; integrated circuit layout; logic CAD; logic design; network routing; programmable logic arrays; field-programmable gate array routing; graph-based strategy; performance-oriented placement; recursive geometric partitioning; source-sink pathlengths; Benchmark testing; Computer science; Delay; Field programmable gate arrays; Integrated circuit interconnections; Logic design; Programmable logic arrays; Routing; Switches; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European

Conference_Location

Brighton

Print_ISBN

0-8186-7156-4

Type

conf

DOI

10.1109/EURDAC.1995.527391

Filename

527391