• DocumentCode
    3539843
  • Title

    MORSE: Multi-objective reconfigurable self-optimizing memory scheduler

  • Author

    Mukundan, Janani ; Martínez, José F.

  • Author_Institution
    Comput. Syst. Lab., Cornell Univ., Ithaca, NY, USA
  • fYear
    2012
  • fDate
    25-29 Feb. 2012
  • Firstpage
    1
  • Lastpage
    12
  • Abstract
    We propose a systematic and general approach to designing self-optimizing memory schedulers that can target arbitrary figures of merit (e.g., performance, throughput, energy, fairness). Using our framework, we instantiate three memory schedulers that target three important metrics: performance and energy efficiency of parallel workloads, as well as throughput/fairness of multiprogrammed workloads. Our experiments show that the resulting hardware significantly outperforms the state of the art in all cases.
  • Keywords
    DRAM chips; learning (artificial intelligence); power aware computing; scheduling; MORSE; figures of merit; multiprogrammed workload throughput-fairness; objective reconfigurable selfoptimizing memory scheduler; parallel workload energy efficiency; parallel workload performance; Genetic algorithms; Hardware; Pipelines; Random access memory; Throughput; Timing; Training;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computer Architecture (HPCA), 2012 IEEE 18th International Symposium on
  • Conference_Location
    New Orleans, LA
  • ISSN
    1530-0897
  • Print_ISBN
    978-1-4673-0827-4
  • Electronic_ISBN
    1530-0897
  • Type

    conf

  • DOI
    10.1109/HPCA.2012.6168945
  • Filename
    6168945