DocumentCode
3540018
Title
Decoupled dynamic cache segmentation
Author
Khan, Samira M. ; Wang, Zhe ; Jiménez, Daniel A.
Author_Institution
Dept. of Comput. Sci., Univ. of Texas at San Antonio, San Antonio, TX, USA
fYear
2012
fDate
25-29 Feb. 2012
Firstpage
1
Lastpage
12
Abstract
The least recently used (LRU) replacement policy performs poorly in the last-level cache (LLC) because temporal locality of memory accesses is filtered by first and second level caches. We propose a cache segmentation technique that dynamically adapts to cache access patterns by predicting the best number of not-yet-referenced and already-referenced blocks in the cache. This technique is independent from the LRU policy so it can work with less expensive replacement policies. It can automatically detect when to bypass blocks to the CPU with no extra overhead. In a 2MB LLC single-core processor with a memory intensive subset of SPEC CPU 2006 benchmarks, it outperforms LRU replacement on average by 5.2% with not-recently-used (NRU) replacement and on average by 2.2% with random replacement. The technique also complements existing shared cache partitioning techniques. Our evaluation with 10 multi-programmed workloads shows that this technique improves performance of an 8MB LLC four-core system on average by 12%, with a random replacement policy requiring only half the space of the LRU policy.
Keywords
cache storage; microprocessor chips; 2MB LLC single-core processor; 8MB LLC four-core system; LRU replacement; SPEC CPU 2006 benchmarks; already-referenced block prediction; cache access patterns; decoupled dynamic cache segmentation; last-level cache; least recently used replacement policy; memory access temporal locality; memory intensive subset; not-recently-used replacement; not-yet-referenced block prediction; off-chip memory latency mitigation; on-chip caches; shared cache partitioning techniques; Benchmark testing; Decision trees; Electronics packaging; Proposals; Resistance; Runtime; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Computer Architecture (HPCA), 2012 IEEE 18th International Symposium on
Conference_Location
New Orleans, LA
ISSN
1530-0897
Print_ISBN
978-1-4673-0827-4
Electronic_ISBN
1530-0897
Type
conf
DOI
10.1109/HPCA.2012.6169030
Filename
6169030
Link To Document