Title :
Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs
Author :
Sundararajan, Karthik T. ; Porpodas, Vasileios ; Jones, Timothy M. ; Topham, Nigel P. ; Franke, Böjrn
Author_Institution :
Sch. of Inf., Univ. of Edinburgh, Edinburgh, UK
Abstract :
Intelligently partitioning the last-level cache within a chip multiprocessor can bring significant performance improvements. Resources are given to the applications that can benefit most from them, restricting each core to a number of logical cache ways. However, although overall performance is increased, existing schemes fail to consider energy saving when making their partitioning decisions. This paper presents Cooperative Partitioning, a runtime partitioning scheme that reduces both dynamic and static energy while maintaining high performance. It works by enforcing cached data to be way-aligned, so that a way is owned by a single core at any time. Cores cooperate with each other to migrate ways between themselves after partitioning decisions have been made. Upon access to the cache, a core needs only to consult the ways that it owns to find its data, saving dynamic energy. Unused ways can be power-gated for static energy saving. We evaluate our approach on two-core and four-core systems, showing that we obtain average dynamic and static energy savings of 35% and 25% compared to a fixed partitioning scheme. In addition, Cooperative Partitioning maintains high performance while transferring ways five times faster than an existing state-of-the-art technique.
Keywords :
cache storage; microprocessor chips; multiprocessing systems; performance evaluation; chip multiprocessor; cooperative partitioning; dynamic energy saving; energy-efficient cache partitioning; four-core systems; high-performance CMP; last-level cache; logical cache; partitioning decisions; performance improvements; runtime partitioning scheme; static energy saving; two-core systems; Hardware; Monitoring; Partitioning algorithms; Registers; Resource management; Vectors; Wireless application protocol;
Conference_Titel :
High Performance Computer Architecture (HPCA), 2012 IEEE 18th International Symposium on
Conference_Location :
New Orleans, LA
Print_ISBN :
978-1-4673-0827-4
Electronic_ISBN :
1530-0897
DOI :
10.1109/HPCA.2012.6169036