• DocumentCode
    3540076
  • Title

    Dynamically heterogeneous cores through 3D resource pooling

  • Author

    Homayoun, Houman ; Kontorinis, Vasileios ; Shayan, Amirali ; Lin, Ta-Wei ; Tullsen, Dean M.

  • fYear
    2012
  • fDate
    25-29 Feb. 2012
  • Firstpage
    1
  • Lastpage
    12
  • Abstract
    This paper describes an architecture for a dynamically heterogeneous processor architecture leveraging 3D stacking technology. Unlike prior work in the 2D plane, the extra dimension makes it possible to share resources at a fine granularity between vertically stacked cores. As a result, each core can grow or shrink resources, as needed by the code running on the core. This architecture, therefore, enables runtime customization of cores at a fine granularity and enables efficient execution at both high and low levels of thread parallelism. This architecture achieves performance gains from 9-41%, depending on the number of executing threads, and gains significant advantage in energy efficiency of up to 43%.
  • Keywords
    computer architecture; multiprocessing systems; 3D resource pooling; 3D stacking technology; core runtime customization; dynamically heterogeneous cores; dynamically heterogeneous processor architecture; energy efficiency; multicore architectures; thread parallelism; Delay; Multicore processing; Multiplexing; Pipelines; Radio frequency; Registers; Three dimensional displays;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computer Architecture (HPCA), 2012 IEEE 18th International Symposium on
  • Conference_Location
    New Orleans, LA
  • ISSN
    1530-0897
  • Print_ISBN
    978-1-4673-0827-4
  • Electronic_ISBN
    1530-0897
  • Type

    conf

  • DOI
    10.1109/HPCA.2012.6169037
  • Filename
    6169037