Title :
A memory selection algorithm for high-performance pipelines
Author :
Bakshi, Smita ; Gajski, Daniel D.
Author_Institution :
Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
Abstract :
In order to perform high-throughput DSP computations that are predominantly vector or array based, it is essential that the memory organization satisfy both the storage and the performance requirements of the design. In this paper, we present an algorithm to select a memory organization, in addition to selecting a pipeline and other datapath components, given performance constraints. We also conduct experiments to give a quantitative measure of the impact of memory selection on DSP design
Keywords :
circuit CAD; data flow graphs; digital signal processing chips; integrated circuit design; pipeline processing; datapath components; digital signal processor design; high-performance pipelines; high-throughput DSP computations; memory organization; memory selection algorithm; performance requirements; Character generation; Computer science; Costs; Delay; Digital signal processing; High performance computing; Libraries; Pipeline processing; Read-write memory; Throughput;
Conference_Titel :
Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European
Conference_Location :
Brighton
Print_ISBN :
0-8186-7156-4
DOI :
10.1109/EURDAC.1995.527397
